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swisstraeng t1_j07mua3 wrote

(friendly reminder that 2nm is a marketing name and has nothing to do with actual values compared to back when it used to, it's now just a name for a fabrication process)

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Gavri3l t1_j07oc9n wrote

Thanks for this. I was really wondering how they managed to get past the quantum tunneling problem.

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swisstraeng t1_j08a2s9 wrote

Well, they didn't. In reality the 2nm process has an expected gate size of around 45nm.

That doesn't mean they aren't finding cool ways to make the chips even more compact. Lots of less known terms like GAAFET. (some kind of vertical 3D transitors)

But the main issue with all of this, is that the prices to manufacture a single chip is higher and higher. Since now it's not a matter of size, but also of fabrication complexity and time.

If I were to guess, we'll get slowly stuck in 2025-2030 era regarding our current technology. I think this will be when we'll need to use alternatives, more power efficient ARM architecture, which is what Apple is already using for its M1 and M2 chips.

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orincoro t1_j08c6qx wrote

Yeah, I thought I read this, that the obvious next step is to just build the wafers in a 3D architecture, but it’s super complicated to fabricate.

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IlIIlllIIlllllI t1_j08pupi wrote

heat is a bigger problem

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Hodr t1_j0bvehy wrote

Heat is more of a materials issue. Once they hit the wall they can move to GaAs or other semiconductors.

The only reason we still use silicon is the existing infrastructure and the relative abundance of the element.

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swisstraeng t1_j09a5ge wrote

Yeah, and the main issue is that, when you add layers on top of layers, you are less and less flat. And at some point you're a whole layer wrong, so you have to do long and expensive processes to try to flatten the thing again.

Cooling is partially an issue, but that's also because CPU/GPU manufacturers push their chips to their limits in an attempt to make them appear better. And end up selling stuff like RTX4090 that is clocked way too high and end up eating 600W, when it could have 90% of the performances for 300W. But hey. They're not the ones paying the power bill.

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orincoro t1_j0c7tzb wrote

I wonder how much electricity globally is consumed by needlessly overclocked GPUs.

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swisstraeng t1_j0ei32s wrote

Surprisingly not much. If we only look at industry grade hardware. Consumers? Yeah, a lot is wasted.

All server and industrial stuff is actually not too bad. For example, the chip used in the RTX 4090 is also used in a Quadro card.

It is the AD102 chip. Used in the RTX 6000 Ada gpu, which has only 300W TDP compared to the RTX 4090 that has 450W and is pushed to 600W sometimes. Or worse, 800W in the RTX 4090ti.

We're talking about the same chip and a 300W versus 800W difference.

Anyone using a rtx 4090ti is wasting 500W into a bit of extra computing power.

But hey, kwh costs about 0.25euros in the EU depending where you live. This means, you pay 1 euro every 8h of use for a rtx4090ti that could be saved by downclocking the card.

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SneakyCrouton t1_j09z32d wrote

See that's just a marketing name for it, it's actually just a 2D transistor but they draw a little D on there for legality purposes.

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Jaohni t1_j09jjfj wrote

PSA: ISA =/= implementation.

While it was common to suggest in the late 90s and early 2000s that there was a strong distinction between CISC and RISC styles of architecture, owing to CISC having a wide variety of purpose built instructions that aided in accomplishing specific tasks quickly, while RISC would have fewer transistors sitting around doing nothing (idle transistors do still consume some power, btw) as a consequence of bloated instruction sets, in reality, modern ISAs have a mix of CISC and RISC philosophies built in, and more important than a core being ARM or x86, is the way that core is implemented.

In reality, if you look at a variety of implementations of ARM cores, there actually isn't as big an efficiency improvement gen over gen as you would expect, as seen in the Snapdragon 865, 870, 888, and 8 gen 1 all performing relatively closely in longer tasks (though they do benchmark quite differently in benchmarks that test a series of tasks in very short bursts), and actually not being that out of line with certain x86 chips, such as something like a 5800X3D (were one to extrapolate its performance when compared to a 5800X power limited to similar wattage to the SD SoCs), or say, a Ryzen 6800U processor power limited to 5W.

​

That's not to say that there isn't ARM IP out there that can be beneficial to improving performance at lower power draw, but I'd just like to highlight that a lot of the improvements you see in Apple Silicon aren't necessarily down to it being ARM, but due to it being highly custom, and due to Apple having varying degrees of control over A) the hardware, B) the drivers / OS / software stack, and C) the actual apps themselves. If you're able to optomize your CPU architecture for specific APIs, programming languages, use cases, and operating systems, there's a lot of unique levers you can pull as a whole ecosystem, as opposed to say, just a platform agnostic CPU vendor.

Another thing to note is that while Apple saw a very respectable increase when jumping from Intel to their in house M1 chips, it's not entirely a fair comparison between x86 and ARM as instruction sets, as the Intel implementation was implemented on a fairly inferior node (14 nanometer IIRC), while the M1 series was implemented on a 5nm family node, or possibly more advanced. When taking this into account, and comparing the Intel versus M1 macs, you may want to remove anywhere between 80 to 120% of the performance per watt improvements to get a rough idea of the expected impact of the node, with what's left being a combination of the various ecosystem controls Apple has available.

When compared to carefully undervolted Raptor Lake chips, or equally carefully managed Zen 4 processors, the Apple SoCs, while respectable in what they do (and being respectable as a result of many things not owing to their ARM ISA), they aren't alien tech or anything; they're simply a well designed chip.

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frozo124 t1_j09mnnx wrote

It’s true. I work for ASML and things keep getting smaller

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Ultra-Metal t1_j093vt3 wrote

Well, you have to do that for the gate until they come up with something better. Quantum tunneling is very much a thing at this size.

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Mango1666 t1_j08v67v wrote

idk if gaafet will come to consumers in the capacity finfet and mosfet have reached, gaa is a very supply limited substance in comparison!

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jjayzx t1_j08zqx2 wrote

What do mean substance? GAAFET(Gate All Around FET) is a design, not a material.

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swisstraeng t1_j09bv7d wrote

True that it's not a material, BUT there is a valid point that, such 3D ways of doing transistors are expensive to manufacture.

And we, consumers, don't like expensive things. We want performance/price most of the time.

Not a lot of us would be ready for a 4000$ CPU if it meant 30% better perfs over a 900$ CPU.

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jjayzx t1_j09ddkj wrote

Different designs is how things have been moving forward and how they've been targeting the performance/price ratio. If the device does not require much processing power there are other processors still made on older nodes for a lower price point. The majority of pricing is in the machines, wafers and yields.

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dreamwavedev t1_j0abb8c wrote

I think you might mean GaN which is a different semiconductor material they're using in some power supplies.

GAA stands for gate-all-around and describes the geometry of the transistors (the gate surrounds the channel on all sides, FinFET was just surrounding it on 3 side) not what they're made of

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Phyltre t1_j082kzr wrote

I love when marketing does stuff like "etymology doesn't real, sure the acronym/initialism used to have a meaning but we've retroactively altered it--now KFC doesn't stand for anything." Feels inherently dishonest. You want it to not stand for something, change the name from the characters that do have a history of standing for something. Connotations aren't a matter of explicit unilateral control.

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tr3v1n t1_j08m90j wrote

> Feels inherently dishonest.

It is dishonest, but it also stems from the fact that people got so focused on the numbers that they kept shrinking them because otherwise people wouldn't think there are improvements. If I remember correctly, the number itself was never actually super accurate as the different processes would measure things differently.

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hellhoundtheone t1_j07oers wrote

Are you saying they can produce 2 NM Chips but that doesn’t mean those chips are great ?

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MuhCrea t1_j07q1st wrote

He's saying a 2nm chip doesn't actually measure as 2nm

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rgpmtori t1_j08a9pa wrote

Normally nm means nano meter, it used to be very important to have smaller and smaller sizes for a variety of reasons which improved speed of computers. Ability to produce chips at a smaller nm meant drastic performance improvements like 15 years ago

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Sirisian t1_j07zhey wrote

Just to be clear the nodes do refer to upgrades generally. So both speed and power usage gains. Just as things get closer to literally buildings with atoms the terminology falls apart. The small structures are 3D arrangements, so one measurement doesn't capture things anyway. Back when things were larger (like a decade ago) it made a lot more sense.

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BoltTusk t1_j08eeby wrote

What’s “Intel 18A” then? Not 18 Angstroms?

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swisstraeng t1_j09ahok wrote

Indeed.

1 Angstrom is 0.1nm, and it's first of all completely dumb to use non-standard units, when they could have said 100pm instead.

Intel just ran out of numbers to write, so they used the next available scale: angstrom.

But again, that's just a marketing number.

Intel calls it 18A. TSCM calls it N2, samsung calls it 2GAP. But all those fancy names are just factory processes. Ways to make silicon chips. Those processes are currently done in laboratories and being researched, and are expected to be used around 2025 for production.

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WHAT_DID_YOU_DO t1_j09o1el wrote

TBF to angstrom that is the length of atomic bonds so it’s a lot easier to say a carbon atom is a little over an angstrom than 130 pm

Agreed on most other non-standard measurements though

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Arodg25 t1_j0969zp wrote

any idea why they choose to make this confusing?

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swisstraeng t1_j09967i wrote

Simply put: Engineers said they can't make it smaller, it didn't stop marketing people that thought it was a good idea.

It's as dumb as 2666Mhz ram, that in reality is clocked at 1333MHz, and 2666's proper unit of measurement is MT/s.

Why? Because DDRx ram stands for double data rate. Marketing wanted to use larger numbers because it sounded like it'd sell more ram.

They ended up confusing everyone. Again.

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Optimistic__Elephant t1_j09rezs wrote

Also how you end up with nonsense like this.

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Aetherdestroyer t1_j0axlmf wrote

What is the problem with that?

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eldelshell t1_j0be2j0 wrote

Once upon a time, shaves only had one blade and then, the race to add as many blades as possible started... Is a 10 blade shave better? No, but it's all marketing (my shave has 10 blades! I'm alpha af you single blade pleb)

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Demibolt t1_j0ebxcd wrote

There actually are a lot of interesting reasons for the addition of additional, smaller blades instead of just 1 larger and very sharp blade.

But despite the marketing bs, basically more blades makes it easier for someone to get a close shave while reducing the chance of irritation - while also decreasing product durability. which are all positives to them.

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InternetUnexplorer t1_j0bdx4g wrote

I feel like it kind of makes sense for DDR though? Even if it's not technically correct I feel like the reasoning is pretty straightforward. I don't mind the process names either though, so maybe that's it's just because I'm used to it…

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Yancy_Farnesworth t1_j09xl5d wrote

> it's now just a name for a fabrication process

Yes and no. The process name is supposed to describe an improvement in transistor density now. As in for the same company, the next node is some % improvement over the previous one. They did this because below 7nm the nm measurement became even more meaningless for indicating transistor size/density.

> has nothing to do with actual values compared to back when it used to

Even when the measurement applied to the smallest "feature size", it still didn't describe the size of the actual transistors or transistor density. For example, Intel 10nm was more transistor dense then TSMC's 7nm process. Intel's 7nm process was targeting a higher density than TSMC's 5nm process. Intel fell behind TSMC because they tried to do it on DUV machines rather than EUV, which set them back years as TSMC wound up getting access to EUV equipment first. Hell, even with 7nm, TSMC's was better than Samsung's equivalent process.

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kiwifuel t1_j08eix1 wrote

I don’t think that’s true. Nm (logic gage size) has to do with transistor density. And it is one of several important factors in performance.

I think the average density coming out of a foundry is somewhere between 7 and 14. A foundry i visited in the Texas is pushing 12 nm. Intel and AMD do 7 and 5nm respectively.

2nm is nearing the physical limit. And will serve as a bottle neck in future design. It’s pretty neat. It’s only a few atoms wide.

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g0ndsman t1_j08u6b4 wrote

I don't think the feature size of the technology is 2 nm. The performance might being line with a theoretical scaled 2 nm technology in at least some aspects, but transistors will be much bigger than that. All technologies stopped using actual transistor size (more precisely channel length) years ago as we moved away from planar transistors.

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Murgos- t1_j0905kj wrote

Lambda used to mean the smallest size feature that could be reliably realized in the design. At the same time you still needed margin to carry current and to resolve any imperfections.

So the smallest thing you could make might actually had a minimum requirement of 2Lambda.

I don’t do ASIC gate layout any more but I expect that when they say 7nm now or 5 or whatever they really mean that they can resolve a 7nm feature but you still need 2 or 4 lambda to actually make it work.

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swisstraeng t1_j09bh24 wrote

That's the thing, it is not a few atoms wide. Ask google, you'll learn something. You cannot make a transistor gate of only 5 or 10 atoms, due to quantum tunneling, but I mean, without the fancy quantum name, it just means that, there are probabilities electrons still get the energy to make the jump when we don't want them to. The gate's size is not two nanometers. It's around 40nm. Or bigger.

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