Yes, you can't go smaller than the lattice constant or the material doesn't behave as crystal anymore.

But size isn't really the limitation and there is really no feature about these transistors that is 3nm long. The real kicker is power efficiency.

>reduce power consumption by 30 percent to 35 percent

Power use is the limit. There is obvious supply limit for portables etc. But for all chips, the limit is that you need to cool it and you have to keep it at pretty low temperatures even while it's consuming a lot of power. That means the vent noise goes straight up and that's a deal breaker for home users. In server rooms the noise is less of a problem, but you can still only dump so much power in a little chip before you are unable to carry away the heat.

In practice power use and cooling are what dictate how much computation you can actually do with a chip, so if you want to do more you need more power efficient transistors that don't heat up as much for any given computation.